1. Field of the Invention
The present invention relates to an array-type computer processor including a state control unit and a data-path unit that includes a plurality of processor elements and a plurality of switch elements, which are arranged in a matrix.
2. Description of the Related Art
The current processor units that can perform any of various data processes include the products in practical use that are referred to as the so-called CPU (Central Processing Unit) and MPU (Micro Processor Unit).
The data-processing system using such a processor unit stores in the memory device the various object codes, in which a plurality of operation instructions are described, and the various processed data. The processor unit can read in order the operation instructions and processed data from memory device to serially perform a plurality of data processes.
A single processor unit can thus perform various data processes. The data processes, however, need to perform serially in order the plurality of data processes, and for each of the serial data processes, the processor unit needs to read the operation instructions from the memory device, thereby making it hard to perform complicated data processes at high speed.
On the other hand, if only one data process is to be performed, logical circuits may be formed in hardware for performing the data process, without the necessity of the processor unit reading the plurality of operation instructions from the memory device in order to perform serially the plurality of data processes. The complicated data processes can thus be performed at high speed, but performing only one data process.
That is, the data-processing system that can switch between any object codes can perform various data processes, but not at high speed due to the fixed hardware configuration. On the other hand, the logical circuits in hardware can perform the data processes at high speed, but only one data process due to the fixed object code.
To achieve the above-described problems, the applicants invented an array-type computer processor as the processor unit that can change the hardware configuration according to the software. This array-type computer processor includes a number of small-scale processor elements and switch elements arranged in a matrix, and a data-path unit and state control unit provided in parallel.
Each of the plurality of processor elements can perform individually a data process according to each operation instruction that is individually set. Each of the plurality of switch elements can switch control each of the connections between the plurality of processor elements according to the each operation instruction that is individually set.
The array-type computer processor can thus switch the operation instructions of the plurality of processor elements and the plurality of switch elements to change the hardware configuration to perform the various data processes.
A number of small-scale processor elements as hardware can perform simple data processes in parallel so as to perform complicated data processes at high speed as a whole.
For each operation cycle, the state control unit sequentially switches according to the object code the context of the operation instructions for the plurality of processor elements and the plurality of switch elements as described above, so that the array-type computer processor can continuously perform the parallel processes according to the object code (see, for example, Japanese Patent No. 3269526, Japanese application patent laid-open publication No. 2000-138579, Japanese application patent laid-open publication No. 2000-224025, Japanese application patent laid-open publication No. 2000-232354, Japanese application patent laid-open publication No. 2000-232162, Japanese application patent laid-open publication No. 2003-076668, Japanese application patent laid-open publication No. 2003-099409, and “Introduction to the Configurable, Highly Parallel Computer”, Lawrence Snyder, Purdue University, “IEEE Computer, vol. 15, No. 1, Jan. 1982, pp 47-56”).
A data-processing system is also in practical use that includes the plurality of data-processing devices connected in parallel for sharing the complicated data processes. Such a data-processing system includes a homogeneity-connected type with the plurality of data-processing devices of the same structure connected, and a heterogeneity-connected type with the plurality of data-processing devices of different structures connected.
The homogeneity-connected type of the data-processing system shares one data process in the plurality of data-processing devices of the same structure, thereby allowing for the data process at high parallelism. The heterogeneity-connected type of the data-processing system shares one data process in the plurality of data-processing devices of different types, thereby allowing each data-processing device to perform its special data process. The applicants proposed the heterogeneity-connected type of the data-processing system as described above which includes the combination of the general MPU and the array-type computer processor (see, for example, Japanese application patent laid-open publication 2003-196248).
The array-type computer processor as described above can actually be used after storing data of a computer program of the object code in a program memory, and connecting the program memory to the array-type computer processor via a system bus. The array-type computer processor then obtains data of a computer program from the external program memory, holds the computer program data, and operates according to the held computer program.
The current array-type computer processor has, however, no so-called multitask function, so that it cannot perform process operations according to the plurality of computer programs at a time. To solve this, the multitask function that is realized by conventional general CPU and MPU, for example, may be applied to the array-type computer processor.
The array-type computer processor has, however, a very different hardware structure and operation principle from the general CPU, so that the multitask of the conventional CPU cannot be simply applied to the array-type computer processor. More specifically, the conventional CPU holds in parallel, for example, the plurality of in-process processed data in external high storage capacity RAMs. The conventional CPU thus will not encounter the problem of saving the in-process processed data, even when the process operations according to the plurality of computer programs are performed in a time-sharing and a pseudo-simultaneous manner.
The array-type computer processor, however, distributes and holds the processed data by small volumes in a number of processor elements arranged in a matrix, so that the problem of saving the in-process processed data occurs when switching between the plurality of computer programs. Further, the array-type computer processor can switch the internal condition in a hardware manner according to a set of instruction codes of the computer program, so that the problem occurs of saving the internal condition when switching between the plurality of computer programs.